Plenary Speakers

Thursday 24th March

Title: "Reconfigurable Computing for High Performance Networking Applications"

Speaker: Gordon Brebner (Xilinx)

It is now forecast that Terabit Ethernet will be needed in 2015. (A 1 Tb/s data rate means that the estimated memory capacity of a typical human could be transmitted in 24 seconds.) In this talk, Gordon Brebner will give an overview of research which demonstrates that Field Programmable Logic Array (FPGA) devices can be main processing components for 100-200 Gb/s networking, a main event horizon in 2010, and points the way to how techniques might scale (or not) towards a 1 Tb/s transmission rate by 2015. The highly configurable, and reconfigurable, characteristics of such devices make them a unique technology that fits with the requirements for extremely high performance and moreover for flexibility and programmability. Aside from discussing the physical technological properties, the talk will cover work on higher-level programming models that can make the technology more accessible to networking experts, as opposed to hardware/FPGA experts.

Gordon Brebner is a Distinguished Engineer at Xilinx, Inc., the worldwide leader in programmable logic solutions. He works in Xilinx Labs in San José, California, USA, leading an international group researching issues surrounding networked processing systems of the future. Prior to joining Xilinx in 2002, Gordon was the Professor of Computer Systems at the University of Edinburgh in the United Kingdom, directing the Institute for Computing Systems Architecture. He continues to be an Honorary Professor at the University of Edinburgh, is a Ph.D. advisor at Santa Clara University, and is a visiting lecturer at Stanford University. Professor Brebner has been researching in the field of programmable digital systems for over two decades, presenting regularly at, and assisting with the organization of, the major international conferences in the area. He has authored numerous papers and holds many patents.

Friday 25th March

Title: "Biologically-Inspired Massively-Parallel Architectures-a reconfigurable neural modelling platform"

Speaker: Steve Furber (University of Manchester)

The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support large-scale simulations of systems of spiking neurons in biological real time. The architecture is generic and makes minimal assumptions about the network topologies that will be supported, the goal being to offer a fully reconfigurable platform to test hypotheses of brain function whether they arise from neuroscience, psychology, or elsewhere.

Steve Furber BE FRS FREng is the ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester. He received his BA degree in Mathematics in 1974 and his PhD in Aerodynamics in 1980 from the University of Cambridge, England. From 1980 to 1990 he worked in the hardware development group within the R&D department at Acorn Computers Ltd, and was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor. He moved to the University of Manchester in 1990 where his research interests include low-power and asynchronous digital design and neural systems engineering. Steve was awarded a Royal Academy of Engineering Silver Medal in 2003, held a Royal Society Wolfson Research Merit Award from 2004 to 2009 and was awarded the IET Faraday Medal in 2007 and a CBE in 2008. He was a 2010 Millenium Technology Prize Laureate, and was awarded an Honorary DSc by the University of Edinburgh in 2010.